Senior/Principal Digital Design Engineer
Cambridge, full-time, permanent
Salary range:
- Senior Engineer: £66k to £85k
- Principal Engineer: £85k to £103k
- Senior Principal Engineer: £103k to £121k
- dependent on experience and responsibilities
In this role you will have the opportunity to apply your digital design skills to develop high-quality IP covering a broad range of technologies and industry partners. Your work will focus on the OpenTitan project, which has recently landed the first commercially available open silicon root of trust chip and continues to lead in the domains of open silicon and hardware security. OpenTitan designs include a RISC-V CPU core (Ibex), a separate programmable accelerator for cryptographic operations (OTBN), hardware accelerators for block ciphers (AES) and hashing (SHA2/HMAC, SHA3/KMAC), and multiple off-chip I/O interfaces (including USB, I2C, and SPI). You will be a core contributor and potentially tech lead for the next generations of these designs.
You will:
- Contribute to specifications of new designs and extensions of existing designs, finding high-quality and economical solutions to address new and evolving use cases as well as latest industry standards.
- Write RTL, in SystemVerilog, to implement new features and expand and maintain existing features across the OpenTitan IP portfolio.
- Work closely with DV engineers to develop test and coverage plans and assist in debugging regression failures.
- Collaborate with security engineers to develop security hardening features.
- Contribute to verification closure with design expertise as well as DV code contributions when the team is focusing on verification milestones prior to a tape-out or release.
- Actively review contributions to our open source projects.
- Engage with engineers in other OpenTitan partner companies who are responsible for the integration of OpenTitan into new products or for its use in existing products.
- Potentially take the responsibility of a tech lead for the high-quality and timely delivery of IPs and/or subsystems into partner products.
Candidate Requirements
Essential:
5 years+ prior industry experience of digital design work, including RTL work with SystemVerilog.
- Experience of successful full chip design cycles from initial planning over tape-out to bring-up and post-silicon validation.
- Flexibility to contribute also to silicon architecture, system integration, design verification, chip bring-up, and post-silicon testing if the project requires it.
- Confident in providing work estimates, regularly updating a project manager to track progress against the project plan, and delivering work on time.
- Comfortable working with engineers across multiple organisations in multidisciplinary teams.
- Graduate degree (Master’s degree or Doctorate) in a technical discipline relevant for this role (e.g., Electrical Engineering, Computer Science, Information Technology).
Desirable:
- Broad experience range across multiple digital silicon IPs (such as CPU cores, memory subsystems, interconnects, off-chip I/O controllers, cryptographic accelerators).
- Understanding of security countermeasures against physical attacks such as fault injection or side-channel analysis.
- Experience working with the RISC-V ISA or similar instruction set architectures.
- Familiarity with Git and code collaboration using services such as GitHub, GitLab, or Gerrit.
- Programming using Python, C, and/or Rust in automation and frameworks for auto-generating RTL, SW interfaces, and test and system integration harnesses.
For the Principal role:
- Experience with leading a team and/or being a tech lead in a major project.
- Deep expertise in at least one field that is directly relevant for our IP portfolio.
- Significant record of substantial valuable technical contributions that require innovation and sustained excellence.
For the Senior Principal role:
- Experienced leader who has led multiple major projects.
- Demonstrated commercial and legal awareness.
The team is based in Cambridge, UK, amongst the Silicon Fen’s ecosystem of high tech startups. Our office is in the heart of the city and a short walk from the train station.
We do not discriminate against any employee or candidate because of race, colour, sex, age, national origin, religion, sexual orientation, gender identity, disability, or any other protected characteristic.
Please let us know if you need any adjustments made to the application or selection process so you can do your best. We will be happy to help.
