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Snap Inc.

ASIC Package Engineer

Posted 2 Days Ago
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Hybrid
2 Locations
Senior level
Hybrid
2 Locations
Senior level
The ASIC Package Engineer will design and prototype packaging solutions for custom silicon, manage packaging partners, and ensure high yield and manufacturability while collaborating across teams.
The summary above was generated by AI

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together. The Company’s three core products are Snapchat, a visual messaging app that enhances your relationships with friends, family, and the world; Lens Studio, an augmented reality platform that powers AR across Snapchat and other services; and its AR glasses, Spectacles.

The Spectacles team is pushing the boundaries of technology to bring people closer together in the real world. Our fifth-generation Spectacles, powered by Snap OS, showcase how standalone, see-through AR glasses make playing, learning, and working better together. 

We’re looking for an ASIC Package Engineer  to join the Wearable Computing Silicon group at Snap Inc! 

What you’ll do: 

You will be responsible for driving our next-generation package design from concept to production. Depending on product needs, you will build solutions ranging from classical FCCSPs to SIP and 3D-stacked packages and modules. As you are embedded in a team that builds the full product (from logic concept to end-user consumer device), you will also contribute to the design of the silicon floorplan, bump map, TSVs, and more. Your activities will include designing ball maps, substrate, interposers,  and  direct management of third party packaging partners. You will also work closely with our New Product Introduction (NPI) team to define qualification requirements  for our products.  In addition you will: 

  • Lead Snap’s packaging efforts for custom silicon development from concept to production.

  • Collaborate with design, engineering and manufacturing teams in the development of custom ASICs used in wearable devices 

  • Bridge custom silicon development and PCB integration, to ensure system constraints such as routing and power delivery are considered in our packaging definition.  

  • Define and Prototype solutions (substrate, interposer, etc) to ensure high yield and manufacturability

  • Select our packaging partners, in collaboration with our Global Supply team 

  • Follow production and analyse manufacturing issues; 

  • Develop qualification plans according to latest industry standards working closely with our NPI team.

  • Identify and mitigate risks in the product introduction process, implementing contingency plans as necessary

  • Be an integral part of a highly diverse international team of skilled engineers and scientists, and a be key driver of the team’s further growth

Knowledge, Skills & Abilities:

  • Ample experience with designing complex packages (FC-CSP, SiP, …), and associated tools.

  • Understanding of signal integrity principles and proven experience in driving and interpreting Power Integrity and Signal Integrity simulations

  • Knowledge of package thermal simulations

  • Deep understanding of various packaging assembly steps

  • You have successfully designed packages for products which are being shipped in volume 

  • Proactive, flexible, team player with can-do attitude and excellent problem analysis skills

  • Proven experience in process development and documentation

  • Excellent written and verbal English communication

Minimum Qualifications:

  • Bsc or MSc degree in related field such as electrical engineering or equivalent years of experience

  • 7+ years of experience in ASIC package development

  • 3+ years of experience in Power integrity and Signal integrity 

  • Excellent Project Management skills

Preferred Qualifications:

  • Familiarity with semiconductor supply chain and logistics management

  • Experience with failure analysis techniques

  • Hands-on experience with troubleshooting packaging yield issues at the factory

  • Experience with common requirement management practices, software engineering tools such as Github, etc.

  • Mandarin speakers is a plus

  • A passion for Snapchat and creativity!

If you have a disability or special need that requires accommodation, please don’t be shy and provide us some information.

"Default Together" Policy at Snap: At Snap Inc. we believe that being together in person helps us build our culture faster, reinforce our values, and serve our community, customers and partners better through dynamic collaboration. To reflect this, we practice a “default together” approach and expect our team members to work in an office 4+ days per week. 

At Snap, we believe that having a team of diverse backgrounds and voices working together will enable us to create innovative products that improve the way people live and communicate. Snap is proud to be an equal opportunity employer, and committed to providing employment opportunities regardless of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, pregnancy, childbirth and breastfeeding, age, sexual orientation, military or veteran status, or any other protected classification, in accordance with applicable federal, state, and local laws. EOE, including disability/vets.

Our Benefits: Snap Inc. is its own community, so we’ve got your back! We do our best to make sure you and your loved ones have everything you need to be happy and healthy, on your own terms. Our benefits are built around your needs and include paid parental leave, comprehensive medical coverage, emotional and mental health support programs, and compensation packages that let you share in Snap’s long-term success!

Top Skills

Asic Design
Fccsp
Power Integrity Analysis
Signal Integrity Analysis
Sip
Thermal Simulations

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